Single-thread optimisation

Where Intel states when a structure of arrays beats an array of structures, strided and hybrid cases included.

Also in §1§4

Measures one kernel in both layouts and traces the gain to the gathers the array-of-structures form forces.

Defines interchange, skewing, reversal and tiling as one family and proves when each keeps a loop nest legal.

Traces the drops in a blocked loop's speed curve to self-interference misses, and shows when copying a tile pays.

Where LLVM lists what its loop and SLP vectorisers accept: interleaving, reductions, if-conversion and runtime checks.

Also in §8

Maps each intrinsic to its instruction and CPUID flag, with the vendor's latency and throughput per microarchitecture.

The normative semantics of every Intel vector instruction, with the masking, rounding and fault rules intrinsics hide.

Also in §5§13

Where Arm explains vector-length-agnostic loops and predication, the model that removes remainder loops entirely.

The specification the NEON and SVE intrinsics come from, so it settles what a compiler must accept and what is a bug.

The normative definition of NEON, SVE and SVE2 instructions and of the scalable vector and predicate register model.

Also in §13

Defines sizeless vector types with run-time dispatch, so one source serves SVE and every fixed-width ISA.

Fixes a batch type per ISA and width, the compile-time vector length model, and still reaches NEON and SVE.

Where shuffle-based lookup replacing a byte loop is worked through step by step, with the measurement method spelt out.

Shows branch-free structural indexing with carry-less multiply and shuffles, measured against conventional parsers.

Where that technique ships, with a kernel per ISA and the harness that keeps its published comparisons reproducible.

Decomposes regexes into string and automaton pieces so both run on SIMD, the design inside the matcher Snort embeds.

Counter evidence that current predictors absorb interpreter dispatch, so a branch removal must be measured, not assumed.

Derives the branch-free integer tricks, division by a constant among them, with proofs rather than as a catalogue.

A worked branchless merge with code whose gain vanishes when the compiler emits no conditional move.

Measures branch-free search over sorted, Eytzinger and B-tree layouts, the winner changing with size and prefetch.

Shows a carry-save adder tree in vector registers beating the dedicated instruction, timed as the minimum of many runs.