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§16 · Real but unproven

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Everything below is real but unproven: no item yet has all three of a written specification, a part you can buy, and a public measurement stating every one of the seven fields. Each line says what would promote it. Vendor multiples never qualify. Last checked 2026-09-15.
criterion 1

A written specification

criterion 2

A part on sale

criterion 3

A public seven-field measurement

Last checked

ISA extensions without a shipped server part 4

  1. 01
    Intel AVX10.2 Architecture Specification manual

    Folds the AVX-512 subsets into one versioned level and adds BF16 and FP8 forms, pending a shipped part and a run.

    promotes when → a shipped part and a run

  2. 02
    Intel Architecture Instruction Set Extensions Programming Reference manual

    Ties APX, with doubled x86 registers, AVX10.2 and AMX FP8 tiles to Diamond Rapids, pending silicon and a public run.

    promotes when → silicon and a public run

  3. 03
    SME in a Neoverse core no link

    SME in a Neoverse core, so far shipped only in client parts, pending a server core that carries it and a public run.

    promotes when → a server core that carries it and a public run

  4. 04
    RISC-V Vector Extension, Version 1.0 manual

    The ratified vector ISA, shipped only as IP and chiplets, pending a socketed server part and a run against Arm or x86.

    promotes when → a socketed server part and a run against Arm or x86

Parts without a public measurement 4

  1. 01
    6th Gen AMD EPYC Server CPUs report

    The Zen 6 server family, so far a press release with no shipped part, pending shipment and a public run against Zen 5.

    promotes when → shipment and a public run against Zen 5

  2. 02
    Intel Xeon 6+ Processors manual

    The E-core-only sockets after Sierra Forest, shipped with vendor multiples footnoted off the page, pending a public run.

    promotes when → a public run

  3. 03
    NVIDIA Vera CPU report

    Custom Arm cores with statically partitioned SMT and no architecture document, pending a specification and a public run.

    promotes when → a specification and a public run

  4. 04
    Arm Neoverse V3 Core Software Optimization Guide manual

    Vendor timing tables for the core shipped in Graviton 5 and previewed in Cobalt 200, pending a public run on the core.

    promotes when → a public run on the core

Memory and interconnect 3

  1. 01
    CXL Specification manual

    Defines memory pooled across hosts on a coherent link, with latency so far estimated, pending a run on a shipped pool.

    promotes when → a run on a shipped pool

  2. 02
    Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices paper

    Measures expansion devices with frequency and SMT fixed, the nearest run to every field, pending compiler and flags.

    promotes when → compiler and flags

  3. 03
    DDR5MDB02 Multiplexed Rank Data Buffer, JESD82-552 manual

    Defines the data buffer behind MRDIMMs, whose vendor bandwidth claims name no method, pending a run against RDIMMs.

    promotes when → a run against RDIMMs

Kernel paths and generated code 4

  1. 01
    Extensible Scheduler Class manual

    Lets a BPF program schedule at run time with safe fallback, once a run against the default scheduler states every field.

    promotes when → a run against the default scheduler states every field

  2. 02
    io_uring zero copy Rx manual

    Lands payloads straight in user memory on header-splitting NICs, pending the implementer's epoll run naming every field.

    promotes when → the implementer's epoll run naming every field

  3. 03
    T-MAC repository

    Table-lookup kernels for low-bit weights, with a baseline stated but no frequency, compiler or flags, pending those.

    promotes when → those

  4. 04
    Faster sorting algorithms discovered using deep reinforcement learning paper

    Generated small sorts shipped in libc++, timed by CPU family with no model, compiler or flags stated, pending those.

    promotes when → those

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