Memory hierarchy

One measured account of DRAM timing, cache geometry, TLBs and prefetchers that sets the padding and prefetch rules.

Also in §1

The origin of the strided-loop method that recovers cache and TLB size, line size, associativity and miss cost.

Names inclusion victims as the cost of an inclusive last-level cache, the case for non-inclusive and victim designs.

The origin of set duelling and bimodal insertion, the adaptive replacement that survives a streaming pass.

Origin of the lockup-free cache, whose miss-status registers keep misses in flight, so a stream beats a chase.

Fixes the paging walk, the page-walk caches, the TLB invalidation rules and what each memory type permits.

Defines the page-walk cache design space and shows why cached partial translations let a walk skip page-table levels.

The origin of the stream buffer that every vendor stream prefetcher descends from, and of the victim cache.

Names each prefetcher and what trains it, and which stop at a page boundary and which cross it.

Also in §1§7

Names an Arm server core's load-side and store-side prefetchers, its TLB levels and the bits that disable them.

Derives store buffers and invalidate queues from the cost of coherence, the reason reordering exists at all.

Also in §1

The store-buffer model of Intel and AMD ordering, tested on hardware, fixing which reorderings a fence pays for.

The formal model Arm adopted into its architecture, and the record of why the non-multicopy-atomic option was dropped.

Measures line-transfer cost between cores by coherence state and distance, the figure behind every contention rule.

The implementers' account of perf c2c, whose worked example reads contended lines, offsets and callers off the report.

Introduces and measures structure splitting and field reordering on real programs, the origin of hot-cold layout rules.

Argues from cache-line utilisation arithmetic that layout must follow the access pattern, the case behind structure of arrays.

Prints a struct's holes, padding and cache-line boundaries from DWARF, so a layout is seen rather than guessed.

Sorts software prefetch into the cases where it helps and hurts, and shows how it mistrains hardware prefetchers.

The kernel's statement of THP: the enabled and defrag knobs, khugepaged, and the counters showing what was obtained.

Measures the fault latency, memory bloat and unfairness that eager THP promotion causes, and shows what removes them.