Hardware generations

Where Intel states what Sapphire Rapids added: larger L2 and L3, DDR5, CXL, AMX and on-die accelerators.

Measures L3 and memory latency across the tiled mesh and the slow clock ramp the vendor overview omits.

The designers' statement of what changed: fewer, larger dies, a bigger shared L3, faster DDR5 and socket links.

Measures per-die L3 under sub-NUMA clustering and the die-crossing cost on Granite Rapids beside Turin.

Bandwidth-bound codes on Sapphire, Emerald and Granite Rapids and Sierra Forest with clocks, SMT and compiler stated.

The designers' account of the Zen 4 core and how it yields Genoa, Genoa-X, Bergamo and Siena.

Tests the same-core claim for Zen 4c: cache latency, clock ceiling and core-to-core paths beside clock-matched Zen 4.

Where AMD states what Zen 5 changed in front end, vector datapath and caches, the core Turin carries.

Also in §2§3

Defines Turin: Zen 5 or Zen 5c dies, which parts double die-to-IO links, NUMA modes and full-width AVX-512.

Measures what wider die-to-IO links and faster DDR5 do for Turin bandwidth, and where latency rose over Genoa.

Where AWS states which Neoverse core, ISA revision, mesh, caches and compiler flag each Graviton generation carries.

Sets the pipeline widths and instruction timings of the core Graviton 4, Grace and Axion share.

Also in §2

States the coherency fabric, LPDDR5X fit and MPAM cache and memory partitioning on Grace.

States the timings and fusion rules of the narrower N line core in Cobalt 100 and Yitian.

Where Ampere states the N1 part: private L2 per core, shared system cache, mesh and DDR4 fit.

Measures Neoverse V2, Golden Cove and Zen 4 in-core at fixed clock, and each socket's clock under vector load.

One SVE workload run on Graviton 3, Graviton 4, Yitian and Axion with compiler, runs and spread stated.

Measures a sustained rename width below the stated one, cache latencies, mesh behaviour and cross-socket cost on V2.

Measures structure sizes, cache latencies and mesh behaviour of N2 on Yitian, the core Cobalt 100 carries.

Puts vendor slides beside measurements of the predictor, small instruction cache, private L2 and long memory latency.