---
title: "16. Watchlist"
url: https://cpuperf.com/watchlist/
source: https://github.com/usamahz/cpu-performance-engineering/blob/deb5a0bac46760503b6f4a2608bdfed470c8532e/README.md#L681
commit: deb5a0bac46760503b6f4a2608bdfed470c8532e
---
## 16. Watchlist

Everything below is real but unproven: no item yet has all three of a written specification, a part you can buy, and a public measurement stating every one of the seven fields. Each line says what would promote it. Vendor multiples never qualify. Last checked **2026-09-15**.

### ISA extensions without a shipped server part

- [Intel AVX10.2 Architecture Specification](https://www.intel.com/content/www/us/en/content-details/828965/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html) - Folds the AVX-512 subsets into one versioned level and adds BF16 and FP8 forms, pending a shipped part and a run.
- [Intel Architecture Instruction Set Extensions Programming Reference](https://www.intel.com/content/www/us/en/content-details/671368/intel-architecture-instruction-set-extensions-programming-reference.html) - Ties APX, with doubled x86 registers, AVX10.2 and AMX FP8 tiles to Diamond Rapids, pending silicon and a public run.
- SME in a Neoverse core, so far shipped only in client parts, pending a server core that carries it and a public run.
- [RISC-V Vector Extension, Version 1.0](https://docs.riscv.org/reference/isa/unpriv/v-st-ext.html) - The ratified vector ISA, shipped only as IP and chiplets, pending a socketed server part and a run against Arm or x86.

### Parts without a public measurement

- [6th Gen AMD EPYC Server CPUs](https://newsroom.amd.com/news/aai-2026-6th-gen-epyc/) - The Zen 6 server family, so far a press release with no shipped part, pending shipment and a public run against Zen 5.
- [Intel Xeon 6+ Processors](https://www.intel.com/content/www/us/en/products/details/processors/xeon/6-plus-series.html) - The E-core-only sockets after Sierra Forest, shipped with vendor multiples footnoted off the page, pending a public run.
- [NVIDIA Vera CPU](https://www.nvidia.com/en-us/data-center/vera-cpu/) - Custom Arm cores with statically partitioned SMT and no architecture document, pending a specification and a public run.
- [Arm Neoverse V3 Core Software Optimization Guide](https://support.arm.com/documentation/109678/latest/) - Vendor timing tables for the core shipped in Graviton 5 and previewed in Cobalt 200, pending a public run on the core.

### Memory and interconnect

- [CXL Specification](https://computeexpresslink.org/cxl-specification/) - Defines memory pooled across hosts on a coherent link, with latency so far estimated, pending a run on a shipped pool.
- [Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices](https://arxiv.org/abs/2303.15375) - Measures expansion devices with frequency and SMT fixed, the nearest run to every field, pending compiler and flags.
- [DDR5MDB02 Multiplexed Rank Data Buffer, JESD82-552](https://www.jedec.org/standards-documents/docs/jesd82-552) - Defines the data buffer behind MRDIMMs, whose vendor bandwidth claims name no method, pending a run against RDIMMs.

### Kernel paths and generated code

- [Extensible Scheduler Class](https://docs.kernel.org/scheduler/sched-ext.html) - Lets a BPF program schedule at run time with safe fallback, once a run against the default scheduler states every field.
- [io_uring zero copy Rx](https://docs.kernel.org/networking/iou-zcrx.html) - Lands payloads straight in user memory on header-splitting NICs, pending the implementer's epoll run naming every field.
- [T-MAC](https://github.com/microsoft/T-MAC) - Table-lookup kernels for low-bit weights, with a baseline stated but no frequency, compiler or flags, pending those.
- [Faster sorting algorithms discovered using deep reinforcement learning](https://www.nature.com/articles/s41586-023-06004-9) - Generated small sorts shipped in libc++, timed by CPU family with no model, compiler or flags stated, pending those.